A. Field of the Invention
The invention described herein relates to methods and devices for reducing the DC offset error voltages commonly found in electronic amplifier circuits.
B. Description of the Related Art
In a typical amplifier circuit such as an operational amplifier, it is desirable to have a zero volt output signal when the inputs are at the same voltage. Due to various sources of error including transistor mismatches and process variations, the output of an amplifier typically is non-zero when a zero volt input signal is applied. This is referred to as a DC offset error voltage. An input offset voltage may be applied to the inputs to eliminate the error and cause the output to go to zero volts.
The amount of correction to apply may be determined by a feedback loop circuit referred to an offset cancellation loop, or an offset loop. The offset loop circuit typically measures the DC voltage at the output of the amplifier and uses this as an error signal. The circuit then applies feedback to subtract (or add) a voltage at the input of the amplifier in order to drive the DC component at the amplifier output to zero. Typically the DC component at the output of the amplifier is measured using a low pass filter with a very low cutoff frequency to ensure that only the DC component is captured.
One such prior art configuration is shown in FIG. 1, where the forward gain amplifier 106 has a gain factor G, and the offset loop cancellation amplifier 102 has a gain factor A. The offset error is modeled as a voltage source 110 applied to the input of ideal amplifier 106. The offset amplifier 102 provides a correction signal to signal summing nodes 108, 112 at the input to forward amplifier 106. Note also that the offset amplifier may include its own error source, modeled as voltage source 104.